1. Field of the Invention
The invention relates to integrated circuits and in particular to logic timing solutions for a pseudo-dynamic latch.
2. Background of the Related Art
One of problem of domino logic circuits is they cannot implement inverting logic (e.g., NAND, NOR, and the like). Accordingly, to implement inverting logic with domino logic circuits, pseudo-dynamic latches can be used to implement inverting logic without additional stage delays, as is known in the art.
A pseudo-dynamic latch is simply a pseudo-dynamic circuit with a latch function, as illustrated in FIG. 1. The pseudo-dynamic latch is known in the art and therefore a detailed description of the circuit will not be presented.
Referring to FIG. 1, select signals S1 and S2 are domino signals, and some of the data inputs are domino, and some are domino-precharge (or buffered domino-precharge), e.g., data signal D1, as will be appreciated by those skilled in the art. The selects S1 and S2 are mutually exclusive, and can arrive relatively earlier than the data signals D1 and D2. When buffered inverted clock signal NCKB is high, it is in the evaluation phase, and when NCKB goes low, it is in hold state just like a conventional latch. However, a special case occurs when none of the select signals S1 and S2 are on. In this case, the circuit may be in the evaluation phase as determined by the status of NCKB, but both the pull-up 130 and pull-down paths 140 and 150 will be off due to the selects being off Therefore, the circuit is in functionally in the hold mode.
As the operating frequency and complexity of logic circuits increase, the potential for timing errors increase and margins decrease. Modern circuit design includes complex modeling of signals with in a circuit and to determine potential errors due to timing problems, such as min-delay, max-delay, and the like. Accordingly, reliable timing is important for reliable operation of logic circuits.
For example, assume a circuit design showed a speed path in one of the domino-precharge signals (e.g., data signal D1). Initially, the domino-precharge signal from domino driver 102 had a buffer 110 used as the deracer. In order to solve the speed path problem, the buffer 110 could be removed. However, subsequent analysis of the design then indicated a violation in the min-delay (i.e., the minimum delay for consistent data latching). An illustration of this problem is provided in the following section in relation to FIG. 2.
Referring to FIG. 2, assume the node PD is high during the evaluation phase. If signal NCKB does not go low by the time the precharge value of data signal D1 arrives (e.g., time 206), then a min-delay situation will occur. As discussed above select signal S1 goes high at time 202, before data signal D1 arrives at time 204. However, since at time 208 precharge data signal D1 is high, select S1 is still high, and NCKB has not gone low due to the skew 201, the new data held 210 is the wrong value. That is at time 208 the wrong value of PD will be latched. In this example, the min-delay was mostly due to the high skew 201 between data signal D1 and the buffered inverted clock signal NCKB. Those skilled in the art will appreciate that the skew can be due to a variety of sources, such as the effects of process variation on the clock, and the like. Therefore, as illustrated in FIG. 2, the related art circuit does not provide for reliable operation.